1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device having a multi-bank arrangement, and more particularly, to a synchronous semiconductor memory device having multiple memory banks that perform at least part of their respective data operations at the same time.
2. Description of the Related Art
To realize high-speed and highly integrated memory devices, a multi-memory bank that is composed of a plurality of memory banks is generally used. Each of the plurality of memory banks comprises a plurality of blocks arranged as a plurality of cell arrays in the column and row directions.
Conventional synchronous semiconductor memory devices having a multi-bank arrangement include a plurality of memory banks that are made up of a plurality of memory cells. Here, each memory bank is activated at a predetermined interval to execute a write operation and a read operation sequentially on a memory bank within the respective memory bank. For instance, after a first memory bank completes the write operation, a second memory bank starts executing the read operation.
FIG. 1 is a timing diagram of the write and read operations of a conventional synchronous semiconductor memory device having multi-bank scheme. Referring to FIG. 1, a write command WR is generated in synchronization with a first clock signal CLK1, and then applied to the synchronous semiconductor memory device. Also, a read command RD is generated in synchronization with a sixth clock signal CLK6, and then is applied to the synchronous semiconductor memory device.
Further, an input data signal DIN, the burst length of which includes four data packets, is fetched by a data strobe signal DQS. Then, the fetched input data is written to a memory cell included in a first memory bank of the synchronous semiconductor memory device in response to a write column selection signal WR_CSL.
After a fifth period of the clock signal CLK has passed, a read command RD is generated in synchronization with a sixth clock signal CLK6, and then, an output data signal (not shown) is read from a memory cell included in a second memory bank of the synchronous semiconductor memory device in response to a read column selection signal RD_CSL. That is, the read operation of the second memory bank starts after the write operation of the first memory bank.
In a conventional synchronous semiconductor memory device having multi-bank scheme, no read command RD is given until five cycles of the clock signal CLK passes after a write command WR is applied to the synchronous semiconductor memory device. That is, a predetermined time delay occurs after the write operation is performed before the read operation begins. During such a time delay, the data bus line of the synchronous semiconductor memory device is in an idle state, and thus, an input/output data signal is not transferred at this time. For this reason, the performance of the synchronous semiconductor memory device may be inefficient.
A suggested solution to this problem is to generate the read command RD in synchronization with a third clock signal CLK3, rather than the sixth clock signal CLK6. However, in this case, a write column selection signal WR_CSL and a read column selection signal RD_CSL are activated at the same time, which would cause malfunction of the synchronous semiconductor memory device.
FIG. 2 is a timing diagram of a conventional synchronous semiconductor memory device having multi-bank scheme in which an error occurs. Referring to FIG. 2, a second write command WR2 is applied to a first memory bank in response to a third clock signal CLK, during which a second write column selection signal WR2-CSL and a read column selection signal RD_CSL are activated at the same time, thus causing the malfunction of the synchronous semiconductor memory device as indicated by CASE1.